In many communication systems, digital signals are presented to communication equipment using one communication protocol and are then generated from the equipment using another communication protocol. For a number of applications in communication environments of this type, the communication protocols involve converting an input stream of the digital signals arriving at a first sampling data rate and permitting another equipment type to receive the signals at a second data sampling rate. Where these data rates are not equal, as in asynchronous data transfer schemes, maintaining accurate communication can be difficult.
The degree of difficulty typically depends on the type of system being used. Typical systems are designed with the expectations that the input and output sampling rates will have known nominal values and that the actual values will not depart significantly from the nominal values. The actual values, however, depend upon the characteristics of various circuits, such as crystal oscillators, which have a range of tolerances. These tolerances cause the actual values of the sampling rates to change over time. Depending on the application and the degree of signal integrity required, these changes can be highly problematic.
Consider, for example, a conventional sampling rate conversion system in which the converter operation is designed according to the known nominal values of the input and output sampling rates. Should the ratio of the input and output sampling rates significantly change from the nominal or expected value, the quality and efficiency of the communication can be severely degraded. For example, if the input sampling rate fs1 is higher than its nominal value, samples will arrive more often than they are processed by the sampling rate conversion system. This discrepancy will typically result in the sampling rate conversion system losing or failing to process some of the input samples.
One previously known technique for addressing this problem involves using a large buffer. A buffer of this type receives input samples at a rate fs1 defined by an input clock. The sampling rate conversion system processes the readily available data input samples stored in the buffer at an output sampling rate fs2. Where the output sampling rate is appreciably less than the rate at which input data are processed, the large buffer is used as an overflow for processed input samples so as to permit output processing at a lower sampling rate. While large buffers mitigate these problems, such buffers are costly and do not eliminate the problems.
Known sampling rate conversion systems also deal with a problem sometimes referred to as frequency offset. Frequency offset is evidenced when the reproduced signal at the output has a frequency that is different from the specified frequency. Frequency offset is a common problem that has been addressed in a variety of ways depending on the design of the sampling rate conversion system. Many of these designs require labor-intensive recalibration of the circuits. Other such designs require retransmission of the data whenever the frequency offset exceeds a certain specified threshold.